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march 2007 rev 5 1/39 1 TDA7580 fm/am digital if sampling processor features fm/am if sampling dsp on-chip analogue to digital converter for 10.7mhz if signal conversion fm channel equalization fm adjacent channel suppression reception enhancement in multipath condition stereo decoder and weak signal processing 2 channel serial audio interface (sai) with sample rate converter i 2 c and buffer spi control interfaces rds filter, demodulator & decoder inter processor transport interface for antenna and tuner diversity front-end agc feedback description the TDA7580 is an integrated circuit implementing an advanced mixed analogue and digital solution, to perform the signal processing of an am/fm channel. the hw & sw architecture has been devised to perform a digital equalization of the fm/am channel, and a real rejection of adjacent channels and any other signals, interfering with the listening of the desired station. in severe multiple path c onditions, the reception is improved to get high quality audio. lqfp64 table 1. device summary part number package packing TDA7580 lqfp64 tube TDA758013tr lqfp64 tape and reel www.st.com
contents TDA7580 2/39 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 block diagram and electrical spe cifications . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 sai interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 rds spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 bspi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 inter processor transport in terface for antenna diversi ty . . . . . . . . . . 26 7i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 24 bit dsp core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.2 dsp peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 clock generation unit (cgu) and oscillator . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 stereo decoder (hwster) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5 serial audio interface (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.6 i 2 c interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7 serial peripheral interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.8 high speed serial synchronous interface (hs 3 i) . . . . . . . . . . . . . . . . . . . 31 8.9 tuner agc keying dac (keydac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.10 asynchronous sample rate converter (asrc) . . . . . . . . . . . . . . . . . . . . . 31 8.11 if band pass analogue to digital converter (ifadc) . . . . . . . . . . . . . 31 8.12 digital down converter (ddc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.13 rds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.14 am/fm detector (cordic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TDA7580 contents 3/39 9.1 electrical application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
list of tables TDA7580 4/39 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. recommended dc operating conditions (tj = -40c to 125c) . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. general interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 table 7. low voltage interface cmos dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. high voltage cmos interface dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. current consumption (tj =-40c to 125c). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. crystal characteristics for 1 and 2 chip load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 table 12. external clock signal on xti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13. dsp core (tj =-40c to 125c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14. fm stereo decoder characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15. sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 16. spi and i 2 c timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 17. sai timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 18. rds spi timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 19. bspi timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 20. hs 3 i timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 21. i 2 c bus timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 table 22. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TDA7580 list of figures 5/39 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. power on and boot sequence using i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. power on and boot sequence using spi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. sai timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6. sai protocol (when: rlrs=0; rrel=0; rckp=1; rdir=0) . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. sai protocol (when: rlrs=1; rrel=0; rckp=1; rdir=1) . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. sai protocol (when: rlrs=0; rrel=0; rckp=0; rdir=0) . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. sai protocol (when: rlrs=0; rrel=1; rckp=1; rdir=0) . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. rds spi timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. rds spi clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. bspi timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. bspi clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. high speed synchronous serial interface - hs 3 i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 15. hs 3 i clocking scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. dsp and rds i 2 c bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. radio mode with external slave audio dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 18. radio mode with external master audio device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 19. audio mode with external slave audio device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 20. application diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 21. package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 22. mechanical, data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
overview TDA7580 6/39 1 overview the algorithm is self-adaptive, thus it requires no ?on-the-field? adjustments after the parameters optimization. the chip embeds a band pass sigma delta analogue to digital converter for 10.7mhz if conversion from a ?tuner device? (the tda7515 is highly recommended). the 24bit dsp allows flexibility in the algorith ms implementation, thus giving some freedom for customer required features. the total processing power offers a significant headroom for customer?s software requirement, even when the channel equalization and the decoding software is running. the program and data memory space can be loaded from an external non volatile memory via i 2 c or spi. the oscillator module works with an external 74 .1mhz quartz crystal. it has very low electro magnetic interference, as it introduces very low distortion, and in any case harmonics fall outside the radio bandwidth. the companion tuner device receives the reference clock through a differential ended interface, which works off the oscillator module by properly dividing down the master clock frequency. that allows the overall system saving an additional crystal for the tuner. after the if conversion, the digitized baseband signal passes through the base band processing section, either fm or am, depending on the listener selection. the fm base band processing comprises of stereo decoder, spike detection and noise blanking. the am noise blanking is fully software implemented. the internal rds filter, demodulator and decoder features complete functions to have the output data available through either i 2 c or spi interface. no dsp support is needed but at start-up, so that rds can work in background and in parallel with other dsp processing. this mode (rds only) allows current consum ption saving for low power application modes. an i 2 c/spi interface is available for any control and communication with the main micro, as well as rds data interface. the dsp spi block embeds a 10 words fifo for both transmit and receive channels, to lighten the dsp task and frequently respond to the interrupt from the control interface. serial audio interface (sai) is the ideal solution for the audio data transfer, both transmit and receive: either master or slave. the flexibility of this module gives a wide choice of different protocols, including i 2 s. two fully independent bidirectional data channels, with separate clocks allows the use of TDA7580 as general purpose digital audio processor. a fully asynchronous sample rate converter (asrc) is available as a peripheral prior to sending audio data out via the sai, so that internal audio sampling rate (~36khz and fm/am mode) can be adapted by upconversion to any external rate. an inter processor transport interface (hs 3 i, high speed synchronous serial interface) is also available for a modular system which implements dual tuner diversity , thus enhancing the overall system performance. it is about a synchronous serial interface which exchanges data up to the mpx rate. it has been designed to reduce the electro magnetic interference toward the sensitive analogue signal from the tuner. general purpose i/o registers are connected to and controlled by the dsp, by means of memory map. a debug and test interface is available for on chip software debug as well as for internal registers read/write operation.
TDA7580 block diagram and electrical specifications 7/39 2 block diagram and electrical specifications figure 1. block diagram warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. table 2. absolute maximum ratings symbol parameter value unit v dd v dd3 power supplies (1) 1. v dd3 refers to all of the nominal 3.3v power supplies (v ddh , v osc , v ddsd ). v dd refers to all of the nominal 1.8v power supplies (v dd , v mtr ). nom. 1.8v nom. 3.3v -0.5 to 2.5 -0.5 to 4.0 v v analog input or output voltage belonging to 3.3v io ring (v ddsd , v ddosc ) -0.5 to 4.0 v digital input or output voltage, 5v tolerant normal (2) failsafe (3) 2. during normal mode operation v dd3 is always available as specified. 3. during fail-safe mode operation v dd3 may be not available. -0.5 to 6.50 -0.5 to 3.80 v v all remaining digital input or output voltage nom. 1.8v nom. 3.3v -0.5 to (vdd+0.5) -0.5 to (vdd3+0.5) v t j operating junction temperature range -40 to 125 c t stg storage temperature -55 to 150 c a/d sai1 sai0 src i2c/spi dac cgu oscillator i2c/spi hs3i rds if digital signal processor
block diagram and electrical specifications TDA7580 8/39 table 3. recommended dc operating conditions (t j = -40c to 125c) symbol parameter comment min. typ. max. unit v dd 1.8v power supply voltage core power supply 1.7 1.80 1.9 v v ddh 3.3v power supply voltage (1) io rings power supply (with g ndh ) 3.15 3.30 3.45 v v osc 3.3v power supply voltage (1) oscillator power supply (gnd osc ) 3.15 3.30 3.45 v v ddsd 3.3v power supply voltage (1) if adc power supply (with g ndsd ) 3.15 3.30 3.45 v v mtr 1.8v power supply voltage dac keying and tuner clock power supply (with gnd mtr ) 1.7 1.80 1.9 v 1. v ddh , v osc , v ddsd are also indicated in this document as v dd3 . all others as v dd. table 4. thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient 68 c/w
TDA7580 block diagram and electrical specifications 9/39 2.1 pin description figure 2. pin connection (top view) 1 vhi 2 vcm 3 vlo 4 inp 5 inn 6 vcmop 7 gndsd 8 gndosc 9 xti 10 xto 11 vddosc 12 vddmtr 13 ckrefp 14 ckrefn 15 agckey 16 gndmtr 48 gnd 47 vdd 46 tst3_lrckr 45 tst2_sckr 44 lrck_lrckt 43 sclk_sckt 42 sdo0 41 vddh 40 gndh 39 tst1_sdi1 38 tst4_sdi0 37 gpio_sdo1 36 testn 35 gnd 34 vdd 33 resetn 64 vddsd 63 vddh 62 gndh 61 vddiso 60 gnd 59 vdd 58 dbout1 57 dbrq1 56 dbin1 55 dbck1 54 vddh 53 gndh 52 dbout0 51 dbrq0 50 dbin0 49 dbck0 32 addr_sd 31 int 30 rds_cs 29 rds_int 28 gndh 27 vddh 26 iqch3 25 iqch2 24 iqch1 23 iqsync 22 vdd 21 gnd 20 scl_sck 19 miso 18 sda_mosi 17 protsel_ss ifadc debug1 osc. tuner dsp /r d s i 2 c /s pi hs 3 i rds sai debug0 ifadc modulator power supply pins pair oscillator power supply pins pair tuner clock out and agc keying dac power supply pins pair core logic 1.8v power supply pins pair i/o ring 3.3v power supply pins pair table 5. pin description n name type description notes after reset 1vhi a internally generated ifadc opamps 2.65v (@v dd =3.3v) reference voltage pin for external filtering it needs external minimum 4.7 f ceramic capacitor 2vcm a internally generated common mode 1.65v (@v dd =3.3v) reference voltage pin for external filtering it needs external minimum 10 f ceramic capacitor 3vlo a internally generated ifadc opamps 0.65v (@v dd =3.3v) reference voltage pin for external filtering it needs external minimum 4.7 f ceramic capacitor 4 inp a positive if signal input from tuner 2.0vpp @vdd=3.3v 5 inn a negative if signal input from tuner 2.0vpp @vdd=3.3v 6 vcmop - not connected.
block diagram and electrical specifications TDA7580 10/39 7 gndsd g ifadc modulator analogue ground clean ground, to be star connected to voltage regulator ground 8 gndosc g oscillator ground clean ground, to be star connected to voltage regulator ground 9xti i high impedance oscillator input (quartz connection) or clock input when in antenna diversity slave mode maximum voltage swing is vdd=3.3v 10 xto o low impedance oscillator output (quartz connection) 11 vddosc p oscillator power supply 3.3v 12 vddmtr p tuner reference clock and agc keying dac power supply 1.8v 13 ckrefp b tuner reference clock positive output. fm 100khz am eu 18khz with internal pull-up, on at reset [pp] output 14 ckrefn b tuner reference clock negative output. fm 100khz am eu 18khz with internal pull-up, on at reset [pp] output 15 agckey a dac output for tuner agc keying 1.5kohm 30% output impedance. 1vpp 1% output dynamic range 16 gndmtr g ground of the tuner reference clock buffer and the agc keying dac 17 protsel_ss b dsp0 gpio for control serial interface (low: spi or high: i 2 c) selection at device bootstrap. in spi protocol mode, after boot procedure, spi slave select, otherwise dsp0 gpio0 dsp0 gpio0 5v tolerant with internal pull-up, on at reset [pp] input 18 sda_mosi b control serial interface and rds io: - spi mode: slave data in or master data out for main spi & rds spi data in - i 2 c mode: data for main i 2 c or rds i 2 c 5v tolerant with internal pull-up, on at reset [pp] input 19 miso b spi slave data out or master data in for main spi and rds spi data out dsp0 gpio1 5v tolerant. with internal pull-up, on at reset [pp] input 20 scl_sck b bit clock for control serial interface and rds 5v tolerant. with internal pull-up, on at reset [pp] input table 5. pin description (continued) n name type description notes after reset
TDA7580 block diagram and electrical specifications 11/39 21 gnd g digital core power ground 22 vdd p digital core power supply 1.8v 23 iqsync b high speed synchronous serial interface (hs 3 i) clock if hs 3 i master mode, else dsp1 gpio or dsp1 debug port clock (dbout1) dsp1 gpio0 5v tolerant. with internal pull-up, on at reset input 24 iqch1 b high speed synchronous serial interface (hs 3 i) channel 1 data if hs 3 i master mode, else dsp1 gpio or dsp1 debug port request (dbrq1) dsp1 gpio1 5v tolerant. with internal pull-up, on at reset [pp] input 25 iqch2 b high speed synchronous serial interface (hs 3 i) channel 2 data if hs 3 i master mode, else dsp1 gpio or dsp1 debug port data in (dbin1) dsp1 gpio2 5v tolerant. with internal pull-down, on at reset [pp] input 26 iqch3 b high speed synchronous serial interface (hs 3 i) channel 3 data if hs 3 i master mode, else dsp1 gpio or dsp1 debug port data out (dbck1) dsp1 gpio3 5v tolerant with internal pull-down, on at reset [pp] input 27 vddh p 3.3v io ring power supply (hs 3 i, i 2 c/spi, rds, int) 28 gndh g 3.3v io ring power ground (hs 3 i, i 2 c/spi, rds, int) 29 rds_int b rds interrupt to external main microprocessor in case of traffic information dsp1 gpio4. 5v tolerant, open drain with internal pull-up, on at reset [od] input 30 rds_cs b rds chip select. when resetn rising, if rds_cs 0, the rds?s spi is selected; else rds?s i 2 c dsp1 gpio5. 5v tolerant. with internal pull-up, on at reset [pp] input 31 int i dsp0 external interrupt 5v tolerant. with internal pull-up, on at reset 32 addr_sd b ifs chip master (low) or slave (high) mode selection, latched in upon resetn release. it selects the lsb of the i 2 c addresses. station detector output dsp0 gpio2 5v tolerant with internal pull-down, on at reset [pp] input 33 resetn i chip hardware reset, active low 5v tolerant with internal pull-up 34 vdd p digital power supply 1.8v 35 gnd g digital power ground 36 testn i test enable pin, active low with internal pull-up table 5. pin description (continued) n name type description notes after reset
block diagram and electrical specifications TDA7580 12/39 37 gpio_sdo1 b dsp0 gpio for boot selection or audio sai0 output. 5v tolerant. dsp0 gpio3. with internal pull-up, on at reset [pp] input 38 tst4_sdi0 b audio sai0 data input or test selection pin in test mode 5v tolerant. dsp0 gpio5. with internal pull-up, on at reset [pp] input 39 tst1_sdi1 b dsp0 gpio for boot selection or audio sai1 input. test selection pin in test mode. 5v tolerant. dsp0 gpio4. with internal pull-up, on at reset [pp] input 40 gndh g 3.3v io ring power ground (audio sai, resetn, test pins) 41 vddh p 3.3v io ring power supply (audio sai, resetn, test pins) 42 sdo0 b radio or audio sai0 data output 5v tolerant. with internal pull up, @0v at reset [pp] output 43 sclk_sckt b sai0 receive and transmit bit clock (master or slave with asrc); sai1 transmit bit clock 5v tolerant with internal pull up, on at reset [pp] input 44 lrck_lrckt b sai0 receive and transmit left/right clock (master or slave with asrc); sai1 transmit left/right clock 5v tolerant with internal pull up, on at reset [pp] input 45 tst2_sckr b sai0 transmit bit clock; sai1 receive and transmit bit clock. or test selection pin in test mode 5v tolerant. dsp0 gpio6. with internal pull up, on at reset [pp] input 46 tst3_lrckr b sai0 transmit leftright clock; sai1 receive and transmit bit clock. or test selection pin in test mode dsp0 gpio7. 5v tolerant. with internal pull up, on at reset [pp] input 47 vdd p digital core power supply 1.8v 48 gnd g digital core power ground 49 dbck0 b debug port clock of dsp0 (dbck0) dsp0 gpio. 9. 5v tolerant. with internal pull down, on at reset [pp] input 50 dbin0 b debug port data input of dsp0 (dbin0) dsp0 gpio. 11. 5v tolerant. with internal pull down, on at reset [pp] input 51 dbrq0 b debug port request of dsp0 (dbrq0) dsp0 gpio. 5v tolerant with internal pull up, on at reset [pp] input 52 dbout0 b debug port data output of dsp0 (dbout0) dsp0 gpio10. 5v tolerant. with internal pull up, on at reset [pp] input table 5. pin description (continued) n name type description notes after reset
TDA7580 block diagram and electrical specifications 13/39 53 gndh g 3.3v io ring power ground (debug interface, gpio) 54 vddh p 3.3v io ring power supply (debug interface, gpio) 55 dbck1 b dsp1 debug port clock (dbck1) if hs 3 i master mode, else high speed synchronous serial interface (hs 3 i) channel3 data dsp1 gpio9. 5v tolerant. with internal pull down, on at reset [pp] input 56 dbin1 b dsp1 gpio or dsp1 debug port data in (dbin1) if hs 3 i master mode, else high speed synchronous serial interface (hs 3 i) channel2 data i dsp1 gpio11 5v tolerant with internal pull down, on at reset [pp] input 57 dbrq1 b dsp1 gpio or dsp1 debug port request (dbrq1) if hs 3 i master mode, else high speed synchronous serial interface (hs 3 i) channel1 data 5v tolerant. with internal pull up, on at reset [pp] input 58 dbout1 b dsp1 gpio or dsp1 debug port data out (dbout1) if hs 3 i master mode, else high speed synchronous serial interface (hs 3 i) clock dsp1 gpio10 5v tolerant with internal pull up, on at reset [pp] input 59 vdd p digital core power supply 1.8v 60 gnd g digital core power ground 61 vddiso p 3.3v n-isolation biasing supply clean 3.3v supply to be star connected to voltage regulator 62 gndh g 3.3v io ring power ground (modulator digital section) 63 vddh p 3.3v io ring power supply (modulator digital section) 64 vddsd p 3.3v ifadc modulator analogue power supply clean power supply, to be star connected to 3.3v voltage regulator table 5. pin description (continued) n name type description notes after reset i/o type i/o definition and status p: power supply from voltage regulator g: power ground from voltage regulator a: analogue i/o i: digital input o: digital output b: bidirectional i/o z: high impedance (input) o: logic low output x: undefined output 1: logic high output output pp : push pull / od : open drain
block diagram and electrical specifications TDA7580 14/39 2.2 electrical characteristics table 6. general interface electrical characteristics (t j =-40c to 125c; v dd =1.8v, v dd3 = 3.3v) symbol parameter test condition min. typ. max. unit l ilh low level input current i/os@v dd3 (absolute value) v i = 0v (1) (2) without pull-up-down device 1 a l ihh high level input current i/os@v dd3 (absolute value) v i = v dd3 (1) (2) without pull-up-down device 1 a l il low level input current i/os@v dd (absolute value) v i = 0v (1) (3) (4) without pull-up-down device 1 a l ih high level input current i/os@v dd (absolute value) v i = v dd (1) (3) (4) without pull-up device 1 a i ipdh pull-down current i/os @ v dd3 v i = v dd3 (5) with pull-down device 35 60 85 a i opuh pull-up current i/os @ v dd3 v i = 0v (6) with pull-up device -100 -70 -40 a i opul pull-up current i/os @ v dd v i = 0v (3) with pull-up device -40 -30 -20 a i aihop analogue pin sunk / drawn current on pin1 v i = v dd3 0.95 1.25 1.55 ma v i = 0v -6.25 -5.0 -3.75 ma i acm analogue pin sunk / drawn current on pin 2 v i = v dd3 6.0 8.0 10.0 ma v i = 0v -10.0 -8.0 -6.0 ma i ail analogue pin sunk / drawn current on pin 3 v i = v dd3 3.75 5.0 6.25 ma v i = 0v -1.55 -1.25 -0.95 ma i ain analogue pin sunk / drawn current on pin 4 and pin 5 v i = v dd3 24 32 40 a v i = 0v -40 -32 -24 a i aih6 analogue pin current on pin 6 v o = 0v or v dd3 5 a i aik analogue pin sunk / drawn current on pin 15 v i = v dd 0.8 1.2 1.6 ma v i = 0v (spec absolute value) 1 a i oz tri-state output leakage v o = 0v or v dd3 without pull up / down device (1) 1 a i ozft 5v tolerant tri-state output leakage v o = 0v or v dd (1) 1 a v o = 5v 80 a i latchup i/o latch up current v < 0v, v > v dd 200 ma v esd electrostatic protection leakage, 1 a 2000 v 1. the leakage currents are generally very small, <1na. the value given here, 1ma, is the maximum that can occur after an electrostatic stress on the pin. 2. on pins: 17 to 20, 23 to 26, 29 to 33, 36 to 39, 42 to 46, 49 to 52, 55 to 58. 3. on pins: 13 and 14. 4. same check on the analogue pin 15 ( physically without pull-up-down) 5. on pins: 25, 26, 32, 49, 50, 55, 56 6. on pins: 17 to 20, 23 to 24, 29 to 31, 33, 36 to 39, 42 to 46, 51, 52, 57, 58
TDA7580 block diagram and electrical specifications 15/39 note: 74.1mhz internal dsp clock, at t amb = 25c. current due to external loads not included. table 7. low voltage interface cmos dc electrical characteristics (t j =-40c to 125c; v dd3 = 3.3v) symbol parameter test condition min. typ. max. unit v il low level input voltage 1.70v <= v dd <= 1.90v 0.2*v dd v v ih high level input voltage 1.70v <= v dd <= 1.90v 0.8*v dd v v ol low level output voltage i ol = 4ma (1) 0.15 v v oh high level output voltage i ol = -4ma (1) v dd -0,15 v 1. it is the source/sink current under worst case conditions and reflects the name of the i/o cell according to the drive capability. table 8. high voltage cmos interface dc electrical characteristics (t j =-40c to 125c; v dd =1.8v) symbol parameter test condition min. typ. max. unit v il low level input voltage 3.15v <= v dd3 <= 3.45v 0.8 v v ih high level input voltage 3.15v <= v dd3 <= 3.45v 2.0 v v ol low level output voltage i ol = xma (1) (2) 0.15 v v oh high level output voltage i ol = -xma (1) (2) v dd3 -0.15 v 1. it is the source/sink current under worst case conditions & refl ects the name of the i/o cell according to the drive capabili ty 2. x=4ma for pins 17 to 20, 29, 30, 32, 37 to 39, 42 to 46; x=8ma for pins 23 to 26, 49 to 52, 55 to 58. table 9. current consumption (t j =-40c to 125c) symbol parameter test cond ition min. typ. max. unit i dd current through v dd power supply v dd =1.8v,v dd3 =3.3v all digital blocks working 120 150 ma i ddhdc static current through v ddh power supply v dd =1.8v, v dd3 = 3.3v 10 13 16 ma i ddhac current through v ddh power supply v dd =1.8v, v dd3 = 3.3v i/os working with 5pf load 50 ma i sd current through v sd power supply v dd =1.8v, v dd3 =3.3v 25 35 45 ma i oscdc current through v osc power supply v dd =1.8v, v dd3 =3.3v without quartz 5.5 8 10.5 ma i oscac current through v osc power supply v dd =1.8v, v dd3 =3.3v with quartz 6.5 9 11.5 ma i mtr current through v mtr power supply v dd =1.8v, v dd3 =3.3v 0.5 1.3 2.0 ma
block diagram and electrical specifications TDA7580 16/39 note: the accuracy depends on the quartz freque ncy precision: high stability oscillator table 10. oscillator characteristics (t j =-40c to 125c; v dd =1.7v to 1.9v, v dd3 = 3.15v to 3.45v) symbol parameter test condition min. typ. max. unit f oscfm oscillator frequency (xti/xto) 74.1 mhz table 11. crystal characteristics for 1 and 2 chip load parameter name parameter value 1 chip load 2 chips load temperature range -55c125c -55c125c adjustment tolerance (@ 25c 3c) 30 ppm 30 ppm frequency stability (-20c+70c) 50 ppm 50 ppm aging @ 25c 5 ppm/year 5 ppm/year shunt (static) capacitance [co] <5pf <5pf motional capacitance 1ff 30% 1ff 30% mode of oscillation at-3rd at-3rd resonance resistance < 75 ohm < 45 ohm capacitive load for oscillation frequency = 74.1mhz 10pf 12pf table 12. external clock signal on xti (in case the device is driven by an external clock through the xti pin, the characteristics reported in this table have to be met) parameter name parameter value min typ max unit clock frequency 74.10 mhz frequency stability (-20c+70c) -50 50 ppm clock jitter 10 ps rms start up time 5 ms clock level (sine wave) (1) 1. specified @ xti pin of TDA7580 220 640 mv rms clock level (square wave) (1) 0.50 1.80 v p-p clock duty cycle (square wave) 45 55 % clock rise / fall time (square wave) (1) 500 ps
TDA7580 block diagram and electrical specifications 17/39 mck = 18.525mhz, f sin /f sout = 0.820445366 table 13. dsp core (t j =-40c to 125c) symbol parameter test condition min. typ. max. unit f dspmax maximum dsp clock frequency v dd =1.7v, v dd3 = 3.3v 81.5 mhz table 14. fm stereo decoder characteristics (t j =-40c to 125c; v dd =1.7v to 1.9v, v dd3 = 3.15v to 3.45v; bw for measurements 20hz to 15khz) symbol parameter test cond ition min. typ. max. unit a_ch channel separation (adjustble by sw from 0 to -45db) -45 0 db thd total harmonic distortion 1khz; mono; f=75khz; 0.02 0.04 % (s+n)/n signal plus noise to noise ratio 1khz; mono; f=40khz; 78 80 82 db table 15. sample rate converter (t j =-40c to 125c; v dd =1.7v to 1.9v, v dd3 = 3.15v to 3.45v); bw for measurements 20hz to 20khz symbol parameter test condition min. typ. max. unit thd+n total harmonic distortion + noise 20hz to 20khz, full scale, 16 bit inp. -95 -92 db 20hz to 20khz, full scale, 20 bit inp. -98 -95 db 1 khz full scale, 16 bit inp. -98 -95 db 2 khz full scale, 16 bit inp. -98 -95 db 5 khz full scale, 16 bit inp. -98 -95 db 10 khz full scale, 16 bit inp -98 -95 db 15 khz full scale, 16 bit inp -98 -95 db 1 khz full scale, 20 bit inp. -119 -116 db 2 khz full scale, 20 bit inp. -116 -113 db 5 khz full scale, 20 bit inp. -112 -109 db 10 khz full scale, 20 bit inp -108 -105 db 15 khz full scale, 20 bit inp -105 -102 db dr dynamic range 1 khz -60 db - 16 bit inp. a-weighted 97 100 db fratio = 0.82 1 khz -60 db - 24 bit inp. a-weighted 141 145 db r p pass band ripple from 20hz to 15khz 0.4 0.5 db f ratio sampling frequency in/out ratio fsout = 44.1 khz 0.7 1.13
block diagram and electrical specifications TDA7580 18/39 figure 3. power on and boot sequence using i 2 c figure 4. power on and boot sequence using spi vdd3 vdd int resetn addr_sd protsel_ss ifs slave=1 rds_cs gpio_sdo1 ifs master=0 i 2 c/sp i master=0 i 2 c/spi slave=1 tst1_sdi1 boot rds init sw download tuner data data sda_mosi t int t sw t reson t rsu t rhd t tun t dat t seq t vdd3 t vdd vdd3 vdd int resetn addr_sd protsel_ss ifs slave=1 rds_cs gpio_sdo1 ifs master=0 i 2 c/sp i master=0 i 2 c/spi slave=1 tst1_sdi1 boot rds init sw download tuner data data sda_mosi t int t sw t reson t rsu t rhd t tun t dat t seq t vdd3 t vdd
TDA7580 block diagram and electrical specifications 19/39 table 16. spi and i 2 c timing table (t j =-40c to 125c; v dd =1.7v to 1.9v, v dd3 = 3.15v to 3.45v) timing description min typ max unit t vdd3 rise time of 3.3v supply 1 13 25 ms t vdd rise time of 1.8v supply 1 6 10 ms t int maximux delay for int signal - - 1 ms t reson minimum resetn hold time at 0 after the start-up 40 - - ms t rsu minimum data set-up time 250 s t rhd minimum data hold time 250 s t seq minimum wait time including boot 4 ms t sw minimum wait time before downloading the program software 30 s t tun minimum wait time before downloading the software to the fe 1 s t dat minimum wait time before using interface protocols 1 s
sai interface TDA7580 20/39 3 sai interface figure 5. sai timings note: t dsp = dsp master clock cycle time = 1/f dsp figure 6. sai protocol (when: rlrs=0; rrel=0; rckp=1; rdir=0) table 17. sai timing table (t j =-40c to 125c; v dd =1.7v to 1.9v, v dd3 = 3.15v to 3.45v) c load the values on the table are consistent with a capacitance load on sai lines of 160pf timing description min typ max unit t sckr clock cycle 302 976 ns t dt sckr active edge to data out valid 48 65 ns t lrs lrck setup time 25 ns t lrh lrck hold time 25 ns t sdis sdi setup time 65 ns t sdih sdi hold time 65 ns t sckph sck high time 146 ns t sckpl sck low time 146 ns t sckr t sckpl t dt t sdis t lrs t sckph t lrh t sdih valid lrckr sdi0-1 sckr valid (rckp=0) right left sckr sdi0-1 lrckr lsb(n-1) msb(n) msb-1(n) msb-2(n)
TDA7580 sai interface 21/39 figure 7. sai protocol (when: rlrs=1; rrel=0; rckp=1; rdir=1) figure 8. sai protocol (when: rlrs=0; rrel=0; rckp=0; rdir=0) figure 9. sai protocol (when: rlrs=0; rrel=1; rckp=1; rdir=0) right left sckr sdi0-1 lrckr msb(n-1) lsb(n) lsb+1(n) lsb+2(n) right left sckr sdi0-1 lrckr lsb(n-1) msb(n) msb-1(n) msb-2(n) right left sckr sdi0-1 lrckr lsb(n-1) msb(n) msb-1(n) msb-2(n)
rds spi interface TDA7580 22/39 4 rds spi interface figure 10. rds spi timings table 18. rds spi timing table (t j =-40c to 125c; v dd =1.7v to 1.9v, v dd3 = 3.15v to 3.45v) c load the values on the table are consistent with a capacitance load on rds spi lines of 80pf symbol description min typ max unit slave configured t sclk clock cycle 1240 ns t dtr sclk edge to miso valid 239 365 ns t setup mosi setup time 255 ns t hold mosi hold time 365 ns t sclkh sck high time width 620 ns t sclkl sck low time width 620 ns t sssetup ss setup time 620 ns t sshold ss hold time 620 ns t ssw ss pulse width 1240 ns t sclk t sclkl t dtr t sssetup t setup t sclkh t hold t sshold valid miso ss scl (cpol=0,cpha=0) mosi t ssw
TDA7580 rds spi interface 23/39 figure 11. rds spi clocking scheme sck(#20) ss(#17) (cpol=0,cpha=0) (cpol=0,cpha=1) (cpol=1,cpha=0) (cpol=1,cpha=1) sck(#20) sck(#20) sck(#20) msb6543210 miso(#19) mosi(#18)
bspi interface TDA7580 24/39 5 bspi interface (t j =-40c to 125c; v dd =1.7v to 1.9v, v dd3 = 3.15v to 3.45v) c load the values on the tabl e are consistent with a capacita nce load on bspi lines of 160pf) figure 12. bspi timings table 19. bspi timing table symbol description min typ max unit master configured t sclk clock cycle 184 ns t dtr sclk edge to mosi valid 61 92 ns t setup miso setup time 52 ns t hold miso hold time 52 ns t sclkh sck high time 92 ns t sclkl sck low time 92 ns t sssetup ss setup time 92 ns t sshold ss hold time 92 ns t ssw ss pulse width 184 ns slave configured t sclk clock cycle 238 ns t dtr sclk edge to miso valid 88 119 ns t setup mosi setup time 65 ns t hold mosi hold time 65 ns t sclkh sck high time 119 ns t sclkl sck high low 119 ns t sssetup ss setup time 119 ns t sshold ss hold time 119 ns t ssw ss pulse width 238 ns t sclk t sclkl t dtr t sssetup t setup t sclkh t hold t sshold valid miso ss scl (cpol=0,cpha=0) mosi t ssw
TDA7580 bspi interface 25/39 figure 13. bspi clocking scheme sck(#20) ss(#17) (cpol=0,cpha=0) (cpol=0,cpha=1) (cpol=1,cpha=0) (cpol=1,cpha=1) sck(#20) sck(#20) sck(#20) msb6543210 miso(#19) mosi(#18)
inter processor transport interface for antenna diversity TDA7580 26/39 6 inter processor transport interface for antenna diversity (t j =-40c to 125c; v dd =1.7v to 1.9v, v dd3 = 3.15v to 3.45v) c load . the values on the table are consistent with a capacitance load on hs 3 i lines of 20pf figure 14. high speed synchronous serial interface - hs 3 i figure 15. hs 3 i clocking scheme table 20. hs 3 i timing table note: t dsp = dsp master clock cycle time = 1/f dsp timing description min typ max unit t sclk mbc clock cycle 107.95 107.97 ns t dtr mbc active edge to master data out valid 4 ns t setup mbc active edge to master synch valid 4 ns t hold slave data out setup time 6 ns master bit clock master data out master synch slave data out m2 m3 s0 s1 s2 s3 256 cycles of 74.1mhz t mbcc t mbco master synch master data out master bit clock slave data out t mbcs t sdos
TDA7580 i 2 c timing 27/39 7 i 2 c timing figure 16. dsp and rds i 2 c bus timings table 21. i 2 c bus timing table (t j =-40c to 125c; v dd =1.7v to 1.9v, v dd3 = 3.15v to 3.45v) symbol parameter test condition standard mode i 2 c bus fast mode i 2 c bus unit min. max. min. max. f scl scll clock frequency 0 100 0 400 khz t buf bus free between a stop and start condition 4800 ? 1300 ? ns t hd:sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4800 ? 600 ? ns t low low period of the scl clock 4800 ? 1300 ? ns t high high period of the scl clock 4800 ? 600 ? ns t su:sta set-up time for a repeated start condition 4800 ? 600 ? ns t hd:dat data hold time 0 - 0 900 ns t r rise time of both sda and scl signals cb in pf ? 300 12+0.1c b 300 ns t f fall time of both sda and scl signals cb in pf ? 300 12+0.1c b 300 ns t su;sto set-up time for stop condition 4800 ? 600 ? ns t su:dat data set-up time 250 ? 250 ? ns c b capacitive load for each bus line 10 400 10 400 pf
functional description TDA7580 28/39 8 functional description the TDA7580 ic offers a solution for high performance fm/am car radio receivers. the high processing power allows audio processing of both internal and external audio source. the processing engine is based on a 24bit programmable dsp, with separate banks of program and data rams. a number of hardware modules (peripherals) help in the algorithm implementation of channel equalization and fm/am baseband post processing. the hw architecture allows to perform dual tuner diversity. in this case two TDA7580 are needed: one device must be configurated as master, generates the clock and controls the main data interfaces. the second device becomes the slave and converts the second if path, as well as helps the first chip as co-processor. 8.1 24 bit dsp core some capabilities of the dsp are listed below: single cycle multiply and accumulate with convergent rounding and condition code generation 24 x 24 to 56-bit mac unit double precision multiply scaling and saturation arithmetic 48-bit or 2 x 24-bit parallel moves 64 interrupt vector locations fast or long interrupts possible programmable interrupt priorities and masking repeat instruction and zero overhead do loops hardware stack capable of nesting combinations of 7 do loops or 15 interrupts / subroutines bit manipulation instructions possible on a ll registers and memory locations, also jump on bit test 4 pin serial debug interface debug access to all internal regi sters, buses and memory locations 5 word deep program address history fifo hardware and software breakpoints for both program and data memory accesses debug single stepping, instruction injection and disassembly of program memory
TDA7580 functional description 29/39 8.2 dsp peripherals clock generation unit (cgu) stereo decoder (hwster) serial audio interface (sai) tuner agc keying dac (keydac) programmable i/o interface (i 2 c/bspi) asynchronous sample rate converter (asrc) if band pass sigma delta modulator (ifadc) digital down converter (ddc) discriminator (cordic) rds tuner diversity hs3i the peripherals are mapped in the x memory space. most of them can be handled by interrupt, with software programmable priority. peripherals running at very high rate have direct access to x and y data bus for very fast movement from or to the core, by mean of single cycle instruction. 8.3 clock generation un it (cgu) and oscillator this unit is responsible for supplying all necess ary clocks and synchronization signals to the whole chip. the control status register of this unit contains information about the current working mode (oscillator [master mode] or cloc k buffer [slave mode]), the tu ner clock frequency setting, the general setup of the oscillator. this last function is pe rformed inside the cgu, that establishes using a self trimming algorithm, wh ich is the current values that can bias the oscillator: this feature lets the oscillator be independent from process parameters variation. the values of bias current are stored in the control status register of the cgu: 4 bits for the coarse current steps and 6 bits for the fine current steps. in slave mode the oscillator behaves as a bu ffer: the chip can be then driven using an external clock. the clock divider, placed in this unit, generates the tuner the reference clock and can be programmed for frequencies down to 9khz with selectable duty cycle and from 4.4hz to 9khz with duty cycle 50%. an external clock can drive the xti pin (please see table 12 for reference). 8.4 stereo decoder (hwster) the fully digital hardware stereo decoder does all the signal processing necessary to demodulate an fm mpx signal which is prepared by the channel equalization algorithm in the digital if sampling device, providing pilot tone dependent mono/stereo switching, as well as stereo-blend and highcut functionality. selectable de-emphasis time constant allow the use of this module for different fm radio receiver standards.
functional description TDA7580 30/39 there are built in filters for field strength processing. in order to obtain the maximum flexibility the field strength proc essing and noise cancellation, however, are implemented as software inside the programming dsp, which has to provide control signals for the stages softmute, stereoblend, and highcut. 8.5 serial audio interface (sai) the two sai modules have been em bedded in such a way great flexibility is available in their use. the two modules are fully separate and they each have a receive and a transmit channel, as well as they can be selected as either master or slave. the bit clocks and left & right clocks are routed through the pins, so the audio interface can be chosen to be adapted to a large variety of application. one sai transmit channel can have the asynchronous sample rate converter in front, thus separate different audio rate domains. additional feature are: support of 16/24/32 bit word length programmable left/right clock polarity programmable rising/falling edge of the bit clock for data valid programmable data shift direction, msb or lsb received / transmitted first 8.6 i 2 c interfaces the inter integrated circuit bus is a single bidirectional two wire bus used for efficient inter ic control. all i 2 c bus compatible devices incorporate an on-chip interface which allows them communicate directly with each other via the i 2 c bus. every component hooked up to the i 2 c bus has its own unique address whether it is a cpu, memory or some other complex function chip. each of these chips can act as a receiver and /or transmitter on its functionality. two pins are used to interface both i 2 c of the dsp and rds, which have different internal i 2 c address, thus reducing the on board pin interconnections. 8.7 serial peripheral interfaces the dsp and rds can have this serial interface, alternative to the i 2 c one. dsp and rds spi modules have separate pin for chip select. the dsp spi has a ten 24 bit words deep fifo for both receive and transmit sections, which reduces dsp processing overhead even at high data rate. the serial interface is needed to exchange commands and data over the lan. during an spi transfer, data is transmitted and received simultaneously. a serial clock line synchronizes shifting and sampling of the information on the two serial data lines. a slave select line allows individual selection of a slave spi device. when an spi transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin. the central element in the spi
TDA7580 functional description 31/39 system is the shift register and the read data buffer. the system is single buffered in the transfer direction and double buffered in the receive direction. 8.8 high speed serial synchronous interface (hs 3 i) the high speed serial synchronous interface is a module to send and receive data at high rate (up to 9.25mbit/s per channel) in order to exchange data between 2 separate TDA7580 chip. the exchanged data are related to signals that are used to increase reception quality in car radio systems, which make use of antenna diversity based upon two separate antenna and tuner sections. the channel synchronization clock has a programmable duty cycle, so to reduce in band harmonics noise. 8.9 tuner agc keying dac (keydac) this dac provides the front-end tuner with an analogue signal to be used to control the automatic gain controlled stage, thus giving all time the best voltage dynamic range at the ifadc input. 8.10 asynchronous sample rate converter (asrc) this hardware module provides a very flexible way to adapt the internal audio rate, to the one of an external source. it does not require further work off the dsp. there is no need to explicitly configure the input and the output sample rates, as the asrc solves this problem with an automatic digital ratio locked loop. main features are: automatic tracking of sample frequency fully digital ratio locked loop sampling clock jitter rejection up conversion up to 1:2 ratio linear phase 8.11 if band pass analogue to digital converter (ifadc) the ifadc is a band pass sigma delta a to d converter with sampling rate of 37.05mhz (nominal) and notch frequency of 10.7mhz. the structure is a second order switched capacitor multi bit modulator with self calibration algorithm to adjust the notch frequency. the differential ended input allows 4.0vpp voltage dynamic range, and reduces the inferred noise back to the previous stage (tuner), and in turn gives high rejection to common mode noises. the high linearity (very high imd) is neede d to fulfill good resp onse of the channel equalization algorithm. low thermal and 1/f noise assures high dynamic range.
functional description TDA7580 32/39 8.12 digital down converter (ddc) the ddc module allows to evaluate the in-phase and quadrature components of the incoming digital if signal. the i and q computation is performed by the ddc block, which at the same time shifts down to 0-if frequency the incoming digital signal. after the down conversion the rate is still very high (at the 37.05mhz ra te); a sinck filter samples data down by a factor of 32, decreasing it to 1.1578mhz. an additional decimation is performed by the subsequent fir filters, thus lowering the data rate at the final 289.45khz, being the mpx data rate. 8.13 rds the rds block is an hardware cell able to process rds/rbds signal, intended for recovering the inaudible rds/rbds information which are transmitted by most of fm radio broadcasting stations. it comprises of the following: demodulation of the european radio data system (rds) demodulation of the us radio broadcast data system (rdbs) automatic group and block synchronisation with flywheel mechanism error detection and correction ram buffer with a storage capacity of 24 rds blocks and related status information i 2 c and spi interface, with pins shared with the dsp i 2 c/spi after filtering the oversampled mpx signal, the rds/rdbs demodulator extracts the rds data clock, rds data signal and the quality information. the following rds/rbds decoder synchronizes the bitwise rds stream to a group and block wise information. this processing also includes error detection and error correction algorithms. in addition, an automatic flywheel control avoids exhausting the data exchange between rds/rdbs processor and the host. 8.14 am/fm detector (cordic) the am/fm detector is a fully programmable peripheral used to detect the phase, amplitude and frequency information of an input complex signal (in-phase and quadrature signals). it can be used to demodulate pm, am and fm modulated signals. the detection is performed using a high accuracy cordic algorithm, working essentially as a cartesian to polar transformer. four cordics are available to allow concurrent software calls.
TDA7580 application diagrams 33/39 9 application diagrams figure 17. radio mode with external slave audio dac in this mode an external slave stereo dac, like the st tda7535, can be easily connected and the TDA7580 outputs the audio from radio station at 36khz rate. figure 18. radio mode with external master audio device an external digital audio device is connected externally as a digital audio master, and the internal TDA7580 sample rate converter is responsible for the conversion from internal 36khz to the external audio rate. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 tst3_lrckr 45 tst2_sckr 44 lrck_lrckt 43 sclk_sckt 42 sdo0 41 40 39 tst1_sdi1 38 tst4_sdi0 37 gpio_sdo1 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 8 7 6 5 TDA7580 tda7535 dual dac fs=36khz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 tst3_lrckr 45 tst2_sckr 44 lrck_lrckt 43 sclk_sckt 42 sdo0 41 40 39 tst1_sdi1 38 tst4_sdi0 37 gpio_sdo1 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 TDA7580 external audio receiver fs with its owned audio rate fs
application diagrams TDA7580 34/39 figure 19. audio mode with external slave audio device the 2 stereo channel serial audio interface of the TDA7580 chip allows a very flexible application in which external audio source/sinks can be connected. the example shows an external cd player digital output giving the main fs audio rate of the whole system. this rate is also the one of the external dacs and an adc, being configured as slave. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 tst3_lrckr 45 tst2_sckr 44 lrck_lrckt 43 sclk_sckt 42 sdo0 41 40 39 tst1_sdi1 38 tst4_sdi0 37 gpio_sdo1 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 8 7 6 5 TDA7580 fs=44.1khz 1 2 3 4 8 7 6 5 tda7535 cd player adc analog in fs=44.1khz
TDA7580 application diagrams 35/39 9.1 electrical application scheme the following application diagram is only an ex ample. for real application setup, it is necessary to refer to the application notes. figure 20. application diagram example note: vcmop capacitor (4.7uf) is only needed for ca silicon. this is needed to be consistent with "pin description " in table 6 4.7 m f 10 m f 4.7 m f 4.7 m f 470nf 10nf 220nf 10nf 220pf vdda vda and vdd = 1.8v vdda and vddh = 3.3v (**) range 5.6pf to 10pf depending on board parasitics vda 470 470 470 15pf (*) 1 2 3 6 7 4 44 13 3 2 ifout1 5 vhi vcm vlo vcmop gndsd inp lrck0_lrckt 43 sclk0_sckt r o 51 dbrq0 10k(*) 57 dbrq1 vddh vddh 10k(*) 46 tst3_lrckr additional gpio r o r o r o = 01k w to prevent electromagnetic injection r o 5 6 42 sdout_sdo0 sdata gndd gnda sck fsync 34 vdd 35 gnd 31 ifout2 30 inm 13 frel+ 26 ckrefp 470 14 frel- 25 ckrefn 470 15 16 dagc 28 agckey gndmtr 21 gnd sda_mosi 11 vddosc 22pf sda i 2 c bus 18 sda 23 tda7515 rds_interrupt {put pull-up on board} dsp_interrupt master/slave selection (station detector after reset) (*) optional int 10f vdd 100nf vdd 27 29 31 28 vddh gndh addr_sd 32 scl_sck vdd 22pf scl 20 scl 22 22 vddh vddh rds_cs 30 10f 100nf 100nf vddh vddsd gndh vddh 63 vddh 64 vddiso 61 62 36 testn vddh 41 vddh vddh 10 14 vdda vddd 220nf 10 m f vcm outsl rstn outsr l_radio r_audio vdda 12 9 8 7 47 vdd 48 gnd vdd 10f 470nf 33 resetn 59 vdd 60 gnd vdd 10f 54 vddh 53 gndh vddh 100nf 40 gndh 37 gpio_sdo1 tda7535 so14 TDA7580 tqfp64 gndosc vddmtr xti xt o 8 9 10 12 470nf 5.6 p f (**) 10pf 180r rds _ in t
package marking TDA7580 36/39 10 package marking figure 21. package marking
TDA7580 package information 37/39 11 package information in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 22. mechanical, data and package dimensions outline and mechanical data a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.08mm dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.20 0.0066 0.0086 0.0106 0.0079 c 0.09 0.0035 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 7.50 0.295 e 0.50 0.0197 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 7.50 0.295 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0393 k 0? (min.), 3.5? (min.), 7?(max.) ccc 0.080 0.0031 lqfp64 (10 x 10 x 1.4mm) 0051434 f ccc
revision history TDA7580 38/39 12 revision history table 22. document revision history date revision changes 24-jan-06 1 initial release. 01-jun-04 2 changed the style look following the ?corporate technical publications design guide. changed the maturity from product preview to final. 01-dec-04 3 included legend for i/o definition. included separated specification for the 2 spi (bspi and rds-spi). upgraded all tables with temperature range and electrical / timing parameters. changed description of pin 6 in pin description table. added new sub section titled am/fm detector (cordic). 01-jan-06 4 updated all tables. 09-mar-07 5 package changed, layout and text modifications
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